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PRELIMINARY DATA SHEET
512M bits DDR-II SDRAM
EDE5104GASA (128M words x 4 bits) EDE5108GASA (64M words x 8 bits)
Description
The EDE5104GA is a 512M bits DDR-II SDRAM organized as 33,554,432 words x 4 bits x 4 banks. The EDE5108GA is a 512M bits DDR-II SDRAM organized as 16,777,216 words x 8 bits x 4 banks. It is packaged in 60-ball FBGA package.
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA 1 A VDD NU/ /RDQS VSS B C D
(NC)* (NC)*
2
3
7
8
9
EO
Features
VSSQ /DQS VDDQ DQS VDDQ DQ2 VSSDL /RAS /CAS A2 A6 A11 NC (Top view) VSSQ DQ0 VSSQ CK /CK /CS A0 A4 A8 NC VSS VDD
(NC)*
DQ6 DM/RDQS (NC)* VSSQ (DM)* VDDQ DQ4 DQ1 VDDQ VSSQ DQ3 VSS /WE BA1 A1 A5 A9 NC
DQ7
* 1.8V power supply * Double-data-rate architecture: two data transfers per clock cycle * Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver * DQS is edge aligned with data for READs: centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS * Four internal banks for concurrent operation * Data mask (DM) for write data * Burst lengths: 4 only * /CAS Latency (CL): 3, 4 * Auto precharge operation for each burst access * Auto refresh and self refresh modes * 7.8s maximum average periodic refresh interval * 1.8V (SSTL_18 compatible) I/O * Off-Chip-Driver Impedance Adjustment for better signal quality. * Programmable RDQS, /RDQS output for the compatibility to x 4 organization * /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation. * FBGA package is lead free solder (Sn-Ag-Cu)
VDDQ
(NC)*
DQ5
E VDDL VREF F CKE G NC H A10 J VSS A3 A7 A12 BA0 NC VDD
Document No. E0203E41 (Ver. 4.1) Date Published February 2006 (K) Japan URL: http://www.elpida.com
L
This product became EOL in March, 2004.
Elpida Memory, Inc. 2001-2006
Pr
K L VDD
Note: ( )* marked pins are for EDE5104GA. A0 to A12 BA0, BA1 DQ0 to DQ7 DQS, /DQS RDQS, /RDQS /CS /RAS, /CAS, /WE CKE CK, /CK DM VDD VSS VDDQ VSSQ VREF VDDL VSSDL NC*1 NU*2 Address input Bank select address Data-input/output Differential data strobe Differential data strobe for read Chip select Command input Clock enable Differential Clock input Output mask Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit Reference supply voltage Power for DLL circuit Ground for DLL circuit No connection Not usable
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Notes: 1. Not internally connected with die. 2. Don't connect. Internally connected with die.
uc t
EDE5104GASA, EDE5108GASA
Ordering Information
Part number EDE5104GASA-5A-E EDE5104GASA-4A-E EDE5108GASA-5A-E EDE5108GASA-4A-E Mask version A Organization (words x bits) 128M x 4 64M x 8 Internal Banks 4 Data rate (Mbps) 533 400 533 400 /CAS latency 4 3, 4 4 3, 4 Package 60-ball FBGA
Part Number
E D E 51 04 G A SA - 4A - E
EO
Elpida Memory
Type D: Monolithic Device
Product Code E: DDR-II
Lead Free
Density / Bank 51: 512M /4-bank
Speed 5A: 533Mbps 4A: 400Mbps Package SA: FBGA Die Rev.
Bit Organization 04: x4 08: x8
Voltage, Interface G: 1.8V, SSTL_18
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L Pr od
2
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EDE5104GASA, EDE5108GASA
CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Pin Configurations .........................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Electrical Specifications.................................................................................................................................4 Block Diagram ...............................................................................................................................................9 Pin Function.................................................................................................................................................10 Command Operation ...................................................................................................................................12 Simplified State Diagram .............................................................................................................................19 Operation of DDR-II SDRAM.......................................................................................................................20 Package Drawing ........................................................................................................................................42 Recommended Soldering Conditions..........................................................................................................43
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Preliminary Data Sheet E0203E41 (Ver. 4.1)
L Pr od uc t
3
EDE5104GASA, EDE5108GASA
Electrical Specifications
* All voltages are referenced to VSS (GND) * After power up, wait more than 200s and then execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Power supply voltage Power supply voltage for output Input voltage Output voltage Operating temperature (ambient) Storage temperature Power dissipation Symbol VDD VDDQ VIN VOUT TA TSTG PD IOUT Rating -0.5 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -0.5 to +2.3 0 to +70 -55 to +150 1.0 50 Unit V V V V C C W mA Note 1 1 1 1 1 1 1 1
EO
Short circuit output current
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Caution
Recommended DC Operating Conditions (SSTL_18)
* There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ must be less than or equal to VDD.
Parameter Supply voltage Supply voltage for output Input reference voltage Termination voltage DC input logic high DC input low AC input logic high AC input low Symbol VDD min. Typ. max. 1.9 1.9 Unit V V V V V V V V Notes 4 4 1, 2 3 1.7 1.8
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (dc). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
VDDQ VREF VTT VIH (dc) VIL (dc) VIH (ac) VIL (ac)
Pr
1.7 1.8 0.49 x VDDQ VREF - 0.04 VREF VREF + 0.125 -0.3 VREF + 0.250
0.50 x VDDQ 0.51 x VDDQ VREF + 0.04
od
VDDQ + 0.3V VREF - 0.125 VREF - 0.250
uc
t
4
EDE5104GASA, EDE5108GASA
DC Characteristics 1 (TA = 0 to +70C, VDD, VDDQ = 1.8V 0.1V)
Parameter Operating current (ACT-PRE) Symbol Grade -5A -4A max. 110 100 Unit Test condition one bank; tRC = tRC (min.) ; tCK = tCK (min.) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle one bank; Burst = 4; tRC = tRC (min.) ; CL = 4; tCK = tCK (min.) ; IOUT = 0mA; address and control inputs changing once per clock cycle all banks idle; power-down mode; CKE = VIL (max.); tCK = tCK (min.) /CS = VIH (min.); all banks idle; CKE = VIH (min.); tCK = tCK (min.) ; address and control inputs changing once per clock cycle one bank active; power-down mode; CKE = VIL (max.); tCK = tCK (min.) one bank; active / precharge;/CS = VIH (min.); CKE = VIH (min.); tRC = tRAS max; tCK = tCK (min.); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle one bank; Burst = 4; burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (min.) ; IOUT = 0mA one bank; Burst = 4; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 4; tCK = tCK (min.) tRC = tRFC (min.) CKE = 0.2V
IDD0
mA
Operating current (ACT-READ-PRE) Precharge power-down standby current Idle standby current Active power-down standby current
IDD1
-5A -4A
160 140 25
mA
IDD2P IDD2N IDD3P -5A -4A
mA mA mA
55 45 30
EO
Active standby current Operating current (Burst read operating) Operating current (Burst write operating) Auto-refresh current Self-refresh current Operating current (Bank interleaving) Parameter
IDD3N
-5A -4A
65 55
mA
IDD4R
-5A -4A
225 175
mA
DC Characteristics 2 (TA = 0 to +70C, VDD, VDDQ = 1.8V 0.1V)
Symbol
Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load Output timing measurement reference level VOTR Output minimum sink DC current Output minimum source DC current IOL IOH
L
IDD4W -5A -4A -5A -4A IDD5 IDD6 IDD7 -5A -4A
225 175 270 250 4
mA
mA mA
Pr
440 380 mA VTT + 0.603 VTT - 0.603 0.5 x VDDQ +13.4 -13.4
Four bank interleaving READs (BL4) with auto precharge, tRC = tRC (min.); Address and control inputs change during Active, READ, or WRITE commands.
od
5
Unit V V V mA
Notes
1 3, 4, 2, 4
uc
mA
Note: 1. 2. 3. 4.
The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.9V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT.
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Preliminary Data Sheet E0203E41 (Ver. 4.1)
EDE5104GASA, EDE5108GASA
Pin Capacitance (TA = 25C, VDD, VDDQ = 1.8V 0.1V)
Parameter CLK input pin capacitance Input pin capacitance Input/output pin capacitance Symbol CCK CIN CI/O DQ Pins CK min. 1.5 1.5 3.0 Typ 2.0 2.0 3.5 max. 2.5 2.5 4.0 Unit pF pF pF Notes 1 1 2
Notes: 1. Matching within 0.25pF. 2. Matching within 0.50pF.
AC Characteristics (TA = 0 to +70C, VDD, VDDQ = 1.8V 0.1V, VSS, VSSQ = 0V)
-5A Frequency (Mbps) Parameter 533 Symbol tAC tDQSCK tCH tCL tHP tCK min. -500 -450 0.45 0.45 min. (tCL, tCH) 3750 350 350 0.6 0.35 max. +500 +450 0.55 0.55 8000 -4A 400 min. -600 -500 0.45 0.45 min. (tCL, tCH) 5000 400 400 0.6 0.35 tAC min. max. +600 +500 0.55 0.55 8000 tAC max. tAC max. 350 450 Unit ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK Notes
EO
CK high-level width CK low-level width CK half period Clock cycle time DQ and DM input hold time DQ and DM input setup time DQ hold skew factor DQS input high pulse width DQS input low pulse width Write preamble setup time Write postamble Write preamble Read preamble Read postamble
DQ output access time from CK, /CK DQS output access time from CK, /CK
Control and Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals
DQ/DQS output hold time from DQS Write command to first DQS latching transition
DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time
Address and control input hold time Address and control input setup time
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
tDH tDS tIPW tDIPW tHZ tLZ tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRES tWPST tWPRE tIH tIS tRPRE tRPST
Pr
tAC max. tAC min. tAC max. 300 400 tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 0 0.4 0.25 500 500 0.9 0.4 WL + 0.25 0.6 1.1 0.6
od
tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 0 0.4 0.6 0.25 600 600 0.9 0.4 1.1 0.6
WL + 0.25
uc
tCK tCK ps ps
t
tCK tCK
6
EDE5104GASA, EDE5108GASA
-5A Frequency (Mbps) Parameter Active to precharge command Active to active/auto refresh command time Active to read or write command delay Precharge command period Active to auto-precharge delay Active bank A to active bank B command period Write recovery time Symbol tRAS tRC tRCD tRP tRAP tRRD tWR tDAL tWTR tXSC tXPNR tXPRD tXARD tOIT 533 min. 45 60 15 15 tRCD min. 7.5 15 (tWR/tCK)+ (tRP/tCK) 7.5 200 2 6 - AL 2 0 120 max. 32 7.8 -4A 400 min. 45 65 20 20 tRCD min. 10 15 (tWR/tCK)+ (tRP/tCK) 10 200 2 6 - AL 2 0 120 max. 32 7.8 Unit ns ns ns ns ns ns ns tCK ns tCK tCK tCK tCK ns ns s 2 1 Notes
EO
Auto precharge write recovery + precharge time Internal write to read command delay Exit self refresh to any command Exit power down to any non-read command Exit precharge power down to read command Exit active power down to read command Output impedance test driver delay Auto refresh to active/auto refresh command time Average periodic refresh interval
Note: 1. For each of the terms above, if not already an integer, round to the next highest integer. 2. AL: Additive Latency.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
tRFC
tREFI
Pr
7
od uc t
EDE5104GASA, EDE5108GASA
Test Conditions
tCK
CLK
VSWING
VDD
VX
VREF
VSS
/CLK
tCL
tCH
VDD VIH VIL VREF VSS
EO
t
SLEW = (VIH (ac) - VIL (ac))/t
Measurement point
DQ RT =25
VTT
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Pr od uc t
8
EDE5104GASA, EDE5108GASA
Block Diagram
CK /CK CKE
Clock generator
Bank 3 Bank 2 Bank 1
A0 to A12, BA0, BA1
Mode register
Row address buffer and refresh counter
Row decoder
Memory cell array Bank 0
Command decoder
/CS /RAS /CAS /WE
Control logic
EO
Sense amp.
Column address buffer and burst counter
Column decoder
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Data control circuit
Latch circuit
DQS, /DQS
Pr
CK, /CK
DLL
Input & Output buffer
RDQS, /RDQS
DM
od
DQ
uc t
9
EDE5104GASA, EDE5108GASA
Pin Function
CK, /CK (input pins) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered High. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. /RAS, /CAS, /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered.
EO
[Address Pins Table]
Part number EDE5104GA EDE5108GA Bank 0 Bank 1 Bank 2 Bank 3
A0 to A12 (input pins) Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank.
Address (A0 to A12) Row address AX0 to AX12 AX0 to AX12 Column address AY0 to AY9, AY11, AY12 AY0 to AY9, AY11
A10 (AP) (input pin) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = Low) or all banks (A10 = High). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during mode register set commands. BA0, BA1 (input pins) BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
[Bank Select Signal Table]
BA0 L H L H
Remark: H: VIH. L: VIL.
CKE (input pin) CKE High activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Pr
10
od
BA1 L L H H
uc
t
EDE5104GASA, EDE5108GASA
DM (input pin) DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 configuration, DM function will be disabled when RDQS function is enabled by EMRS. DQ (input/output pins) Bi-directional data bus. DQS, /DQS (input/output pins) Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, centered in write data. Used to capture write data. /DQS can be disabled by EMRS. RDQS, /RDQS (output pins) Differential Data Strobe for READ operation only. DM and RDQS functions are switchable by EMRS. These pins exist only in x8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS. VDD, VSS, VDDQ, VSSQ (power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VDDL and VSSDL (power supply) VDDL and VSSDL are power supply pins for DLL circuits. VREF (Power supply) SSTL_18 reference voltage: (0.50 0.01) x VDDQ
EO
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Pr od uc t
11
EDE5104GASA, EDE5108GASA
Command Operation
Command Truth Table The DDR-II SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE Function Mode register set Extended mode register set Auto (CBR) refresh Entry self refresh Exit self refresh Symbol MRS EMRS REF SELF SELFX PRE PALL ACT WRIT WRITA READ READA NOP Previous Current cycle cycle /CS H H H H L H H H H H H H H x x H L H x x x x x x x x x L H L L L L H L L L L L L L L H x x /RAS /CAS /WE L L L L x L L L H H H H H x x x L L L L x H H H L L L L H x x x L L H H x L L H L L H H H x x x BA1, BA0 A12 to A11 A10 A0 to A9 Notes 1 1 1 1 1 1, 2 1 1, 2 Column 1, 2, 3 Column 1, 2, 3 Column 1, 2, 3 Column 1, 2, 3 x x x x 1 1 1, 4, 5 1, 4, 5
BA0 = 0 and MRS OP Code BA0 = 1 and EMRS OP Code x x x BA x BA BA BA BA BA x x x x x x x x x x x x L H x x x x x
EO
Single bank precharge Precharge all banks Bank activate Write Write with auto precharge Read Read with auto precharge No operation Device deselect Power down mode entry Power down mode exit
Row Address Column L Column H Column L Column H x x x x x x x x
Remark: H = VIH. L = VIL. x = VIH or VIL Notes: 1. All of the DDR-II SDRAM operations are defined by states of /CS, /WE, /RAS, and /CAS at the positive rising edge of the clock. 2. Bank Select (BA0, BA1), determine which bank is to be operated upon. 3. Burst read or write cycle may not be terminated. 4. The Power Down Mode does not perform any refresh operations; therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 5. If /CS is low, then when CKE returns high, no command is registered into the chip for one clock cycle.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
DESL H x x PDEN PDEX
Pr
12
od
uc t
EDE5104GASA, EDE5108GASA
CKE Truth Table
CKE Current state Self refresh Function INVALID Exit self refresh with device deselect Exit self refresh with no operation Illegal Maintain self refresh Power down INVALID Power down mode exit Previous Cycle H L L L L H L L L H H H Current Cycle x H H H L x H H L H H L L L H L x Command /CS x H L L x x H L x H L H L L x x x /RAS x x H /CAS x x H /WE x x H BA1,BA0, A12 to A0 Notes x x x Address x x x x x x Address x x Address x Address H x x x x x x x 5 3 4 x 3 3 1 2 2 1 2 2 2
Command x x x x x x
EO
ILLEGAL All banks idle ILLEGAL
Command except NOP x x x x
Maintain power down mode
Device deselect Refer to the current state truth table Power down
Command x x
Register command begin power H down next cycle Entry self refresh
Command L x x x L x x x
Any state other Refer to operations in the current state truth table than listed above Power down entry
Remark: H = VIH. L = VIL. x = VIH or VIL Notes: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied before any command other than self refresh exit. 3. The inputs (BA1, BA0, A12 to A0) depend on the command that is issued. See the Command Truth Table for more information. 4. The Auto Refresh, Self Refresh mode, and the Mode Register Set modes can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Command Truth Table.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
H H H L
Pr
13
od
uc t
EDE5104GASA, EDE5108GASA
Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM.
Current state Idle /CS H L L L L L L L L /RAS /CAS /WE x H H H H H L L L x H L L L L H H H L L L L x H x H H H L L H L L H H L L x H Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT
Operation Nop or Power down Nop or Power down ILLEGAL ILLEGAL ILLEGAL ILLEGAL Row activating Precharge Precharge all banks Auto refresh Self refresh Mode register accessing Extended mode register accessing Nop Nop Begin Read Begin Read Begin Write Begin Write ILLEGAL Precharge Precharge all banks ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
1 1 1 1
EO
L L L L L L L L x Bank(s) active H L L L L L L L L L L L L Read H L L L L L L L L L L L L L L L L L L L x L L L L L L L
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
2 2 2 2
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA
H
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
H H L L H H L L H L L H H L L H H H L L L L x H L L L L H H H L L L L H H L L x H H H L L H L L H H L L H H H H H
1
Pr
BA, A10 (AP) A10 (AP)
PRE
PALL REF
x x
SELF
BA, MRS-OPCODE
MRS
BA, EMRS-OPCODE
od
EMRS DESL NOP READ ILLEGAL READA WRIT ILLEGAL ILLEGAL WRITA ILLEGAL ILLEGAL ILLEGAL ACT PRE PALL REF SELF MRS EMRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
x x
Continue burst to end -> Row active Continue burst to end -> Row active 1 1 1 1
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
uc
1 1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
t
14
EDE5104GASA, EDE5108GASA
Current state Write /CS H L L L L L L L L L L L L /RAS /CAS /WE x H H H H H L L L L L x H L L L L H H H L L L L x H L L L L x H H H L L H L L H H L L x H H H L L Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS
Operation Continue burst to end -> Write recovering Continue burst to end -> Write recovering ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end -> Precharging Continue burst to end -> Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end ->Write recovering with auto precharge Continue burst to end ->Write recovering with auto precharge
Note
1 1 1 1 1 1
x x
BA, MRS-OPCODE
EO
L L x Read with H auto precharge L H L L L L L L L L L L L Write with auto Precharge H L L L L L L L L L L L L L L L L L L L x L L L L L L L
BA, EMRS-OPCODE EMRS
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
DESL NOP READ READA WRIT WRITA ACT PRE PALL
H H H H
1 1 1 1 1 1
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
H H L L H H L L L L x H L L L L H H H L L L L H H L L x H H H H H H H H L L H L L H H L L
Pr
x x REF SELF MRS
BA, MRS-OPCODE BA, EMRS-OPCODE EMRS
x
DESL
od
NOP READ ILLEGAL READA WRIT ILLEGAL ILLEGAL WRITA ILLEGAL ILLEGAL ACT PRE PALL REF SELF MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA
1 1 1 1 1 1
uc t
BA, A10 (AP) A10 (AP)
x x
BA, MRS-OPCODE
BA, EMRS-OPCODE EMRS
15
EDE5104GASA, EDE5108GASA
Current state Precharging
/CS H L L L L L L L L L L L L
/RAS /CAS /WE x H H H H H L L L L L x H L L L L H H H L L L L x H L L L L x H H H L L H L L H H L L x H H H L L
Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT PRE PALL
Operation Nop -> Enter idle after tRP Nop -> Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter idle after tRP Nop -> Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter bank active after tRCD Nop -> Enter bank active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter bank active after tWR Nop -> Enter bank active after tWR
Note
1 1 1 1 1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
EO
L L x Row activating H L L L L L L L L L L L L Write recovering H L L L L L L L L L L L L L L L L L L L x L L L L L L L
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
H H H H H
1 1 1 1 1
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
H H L L H H L L L L x H L L L L H H H L L L L H H L L x H H H H H H H H L L H L L H H L L
Pr
x x REF SELF MRS
BA, MRS-OPCODE BA, EMRS-OPCODE
EMRS
x
DESL
x
NOP
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA
BA, A10 (AP) A10 (AP)
od
READ ILLEGAL READA WRIT ILLEGAL New write WRITA New write ILLEGAL ACT PRE ILLEGAL PALL REF SELF MRS EMRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
1 1
1 1
uc t
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
16
EDE5104GASA, EDE5108GASA
Current state Write recovering with auto precharge
/CS H L L L L L L L L L L L L
/RAS /CAS /WE x H H H H H L L L L L x H L L L L H H H L L L L x H L L x H H H L L H L L H H L L x H H H L L
Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT PRE PALL
Operation Nop -> Enter bank active after tWR Nop -> Enter bank active after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter idle after tRFC Nop -> Enter idle after tRFC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter idle after tMRD Nop -> Enter idle after tMRD
Note
1 1 1 1 1 1
EO
L L x Refresh H L L L L L L L L L L L L L Mode register accessing H L L L L L L L L L L L L L L L L L L x L L L L L L L
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
H
H H
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
H H L L H H L L H H L L L L x H L L L L H H H L L L L H H L L x H H H H H H H H L L H L L H H L L
Pr
x x REF SELF MRS
BA, MRS-OPCODE BA, EMRS-OPCODE
EMRS
x
DESL
od
NOP READ ILLEGAL READA WRIT ILLEGAL ILLEGAL WRITA ILLEGAL ILLEGAL ACT PRE PALL REF SELF MRS EMRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA
uc t
BA, A10 (AP) A10 (AP)
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
17
EDE5104GASA, EDE5108GASA
Current state Extended Mode
/CS H
/RAS /CAS /WE x H H H H H L L L L L L L x H L L L L H H H L L L L x H H H L L H L L H H L L
Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS
Operation Nop -> Enter idle after tMRD Nop -> Enter idle after tMRD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Note
register accessing L L L L L L L L L L L L
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
EO
Remark: Notes: 1. 2. 3.
H = VIH. L = VIL. x = VIH or VIL This command may be issued for other banks, depending on the state of the banks. All banks must be in "IDLE". All AC timing specs must be met.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L Pr od uc t
18
EDE5104GASA, EDE5108GASA
Simplified State Diagram
Power Applied
POWER ON
PRECHARGE PREALL REFS
SELF REFRESH
REFSX MRS MRS EMRS *NOTE IDLE REFA AUTO REFRESH
EO
CKEL CKEH
ACTIVE POWER DOWN
ACT PRECHARGE POWER DOWN
CKEH
*Note : Except drive mode activated by EMRS, drive mode should be deactivated by EMRS to move to an idle state.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
WRITE WRITA WRITA PRECHARGE
CKEL
WRITE
ROW ACTIVE
READ
Pr
WRITA READA READ READA PRECHARGE PRECHARGE PRECHARGE PRECHARGE PREALL
READ
READA
Simplified State Diagram
od
READA
Automatic sequence Command sequence
uc t
19
EDE5104GASA, EDE5108GASA
Operation of DDR-II SDRAM
Read and write accesses to the DDR-II SDRAM are burst oriented; accesses start at a selected location and continue for the fixed burst length of four in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command is used to select the bank and row to be accessed (BA0, BA1 select the bank; A0 to A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR-II SDRAM must be initialized. The following sections provide detailed information covering device initialization; register definition, command descriptions and device operation. Power On and Initialization DDR-II SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ, but is expected to be nominally coincident with VTT. The DQ and DQS outputs are in the High-Z state, where they remain until driven active in normal operation (by a read access). After all power supply, reference voltages, and the clocks are stable, the DDRII SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought High. Following the NOP command, a Precharge ALL command must be applied. Next a mode register set command must be issued for the extended mode register, to enable the DLL. Then a mode register set command must be issued for the mode register, to reset the DLL and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read command. A Precharge ALL command should be applied, placing the device in the "all banks idle" state. Once in the idle state, two Auto Refresh cycles must be performed. Additionally, a mode register set command for the mode register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR-II SDRAM is ready for normal operation. Failure to follow these steps may lead to unpredictable start-up modes. Power-Up and Initialization Sequence The following sequence is required for power-up and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. 2. Start clock and maintain stable condition for a minimum of 200s. 3. The minimum of 200s after stable power and clock (CK, /CK), apply NOP and take CKE High. 4. Wait tRFC. 5. Issue precharge commands for all banks of the device. 6. Issue EMRS to enable DLL. (To issue DLL Enable command, provide Low to A0, High to BA0 and Low to all of the rest address pins, A1 to A11 and BA1) 7. Issue a mode register set command for DLL reset. The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide High to A8 and Low to BA0) 8. Issue precharge commands for all banks of the device. 9. Issue 2 or more auto-refresh commands. 10. Issue a mode register set command with Low to A8 to initialize device operation. 11. Carry out OCD impedance adjustment (Follow "OCD Flow Chart" in the chapter of Off-Chip Driver (OCD) Impedance Adjustment). Whenever issue extended mode register set command for OCD, keep previous setting of A0 to A6, A0 to A12 and BA1
EO
/CK CK
L
EMRS
Pr
PALL
tRP
od
REF
tRFC
uc
EMRS
Command
PALL
MRS
REF
tRFC
MRS
EMRS
Any command
t
tMRD
2 cycles (min.)
2 cycles (min.) 2 cycles (min.)
2 cycles (min.)
Follow OCD Flowchart
DLL enable
DLL reset
200 cycles (min)
OCD mode set
OCD calibration exit
Power up and Initialization Sequence
Preliminary Data Sheet E0203E41 (Ver. 4.1)
20
EDE5104GASA, EDE5108GASA
Programming the Mode Register For application flexibility, burst type, /CAS latency, DLL reset function are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive /CAS latency, and variable data-output impedance adjustment are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Re-executing the MRS and EMRS Commands can alter contents of the MRS and EMRS. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. After initial power up, the both MRS and EMRS Commands must be issued before read or write cycles may begin. All four banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Either MRS or EMRS Commands are activated by the low signals of /CS, /RAS, /CAS and /WE at the positive edge of the clock. When the bank address 0 (BA0) is low, the DDR-II SDRAM enables the MRS command. When the bank address 0 (BA0) is high, the DDR-II SDRAM enables the EMRS command. The address input data during this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new command may be issued after the mode register set command cycle time (tMRD). MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents.
EO
0*
0
DDR-II SDRAM Mode Register Set [MRS] The mode register stores the data for controlling the various operating modes of DDR-II SDRAM. It controls /CAS latency, burst sequence, test mode, DLL reset and various vendor specific options to make DDR-II SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0, while controlling the state of address pins A0 to A12. The DDR-II SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst address sequence type is defined by A3, and, /CAS latency is defined by A4 to A6. The DDR-II doesn't support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes.
BA1 BA0 A12 A11 A10 A9
A8 0 1
L
0*
tWR
Pr
A8
A7
A6
A5
A4
A3
DLL TM /CAS latency BT
A2
A1
A0
Address field
Burst length*2
Mode register
od
A3 0 1 Burst type Interleave Sequential
DLL reset No Yes
A7 0 1
Mode Test
Burst length A2 0 A1 1 A0 0 BL 4
Normal
tWR
/CAS latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1
BA0 0 1
MRS mode MRS EMRS
A11 0 0 0 0 1 1 1 1
A10 0 0 1 1 0 0 1 1
A9 0 1 0 1 0 1 0 1
tWR 2 3 4
A4 0 1 0 1 0 1 0 1
Latency
Reserved
Reserved Reserved Reserved 3 4
uc
Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
t
*BA1 and A12 are reserved for future use and must be programmed to 0 when setting the mode register.
Mode Register Set (MRS)
Preliminary Data Sheet E0203E41 (Ver. 4.1)
21
EDE5104GASA, EDE5108GASA
DDR-II SDRAM Extended Mode Register Set [EMRS] The extended mode register stores the data for enabling or disabling the DLL, output driver strength and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and High on BA0, while controlling the states of address pins A0 to A12. The DDR-II SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver. A3 to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is used for DQS disable and A11 is used for RDQS enable. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 Address field
EO
0*
1
1
0* RDQS /DQS OCD program RFU Additive latency RFU D.I.C DLL
1
Extended mode register
A11 0 1
L
RDQS enable Disable Enable
MRS mode MRS EMRS
A8 0 0 1 0 1 A7 0 1 0 0 1 Driver(1) DQ High Driver(0) DQ Low Adjust mode Reserved
A1 0 1
A10 0 1
/DQS disable Enable Disable
A0 0 1 DLL enable Enable Disable
Pr
Operation
Additive latency A5 0 0 0 0 1 1 1 1 A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 Latency 0 1 2 3 Reserved Reserved Reserved Reserved
BA0 0 1
od
Driver Size 100% Normal Weak Reserved
Driver impedance adjustment A9 0 0 0 1 1
OCD calibration mode exit
uc t
*Refer to the chapter "Off-chip Driver (OCD) impedance Adjustment" for detailed information
Driver strength control Output Driver Impedance Control
*BA1 and A12 to A15 are reserved for future use, and must be programmed to 0 when setting the extended mode register.
Extended Mode Register Set (EMRS)
Preliminary Data Sheet E0203E41 (Ver. 4.1)
22
EDE5104GASA, EDE5108GASA
Off-Chip Driver (OCD) Impedance Adjustment DDR-II SDRAM supports driver calibration feature and the "OCD Flow Chart " is an example of sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment.
Start EMRS: OCD calibration mode exit
EMRS: Drive(1) DQ ; High
EMRS: Drive(0) DQ ; Low
EO
ALL OK
Test Need calibration
ALL OK
Test Need calibration
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
BL=4 code input to all DQs Inc, Dec, or NOP
EMRS: OCD calibration mode exit
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
EMRS : Enter Adjust Mode
EMRS : Enter Adjust Mode
Pr
End
BL=4 code input to all DQs Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
OCD Flow Chart
od uc t
23
EDE5104GASA, EDE5108GASA
Extended Mode Register Set for OCD Impedance Adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode, all outputs are driven out by DDR-II SDRAM. In drive (1) mode, all DQ signals are driven high. In drive (0) mode, all DQ signals are driven low. In adjust mode, BL = 4 of operation code data must be used. OCD must used to control driver impedance within 18 3 range. [OCD Mode Set Program]
A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 Operation OCD calibration mode exit Drive (1) DQ High Drive (0) DQ Low Adjust mode Reserved
EO
DT0 0 0 0 0 1 0 0 1 1 DT1 0 0 0 1 0 1 1 0 0 Other combinations
OCD Impedance Adjustment OCD impedance adjustment can be done using "EMRS Adjust mode" and input operation code patterns as the table of "OCD Adjustment Program". To adjust output driver impedance, controllers must issue "Adjust mode" command using an EMRS command first, after that drive 4 bits of burst code information to DDR-II SDRAM. For this operation, controllers must drive all DQs to each device. Driver impedance in each DDR-II SDRAM device is adjusted for all DQs simultaneously. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement has no effect. Default setting can be any step within the 16 steps range. [OCD Adjustment Program]
4bits burst data inputs to all DQs
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
DT2 0 0 1 0 0 0 1 0 1
Operation DT3 0 Pull-up driver strength NOP Pull-down driver strength NOP NOP NOP Increase by 1 step Decrease by 1 step Reserved Reserved Reserved Reserved
Pr
1 0 0 0 NOP NOP 1 0 1 0 Reserved Reserved Reserved Reserved Reserved
Increase by 1 step Decrease by 1 step
od
24
uc t
EDE5104GASA, EDE5108GASA
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the "Output Impedance Control Register Set Cycle". For input data pattern for adjustment, DT0 to DT3 is a fixed order and not affected by MRS addressing mode (i.e. sequential or interleave).
/CK CK
Command
EMRS
NOP
WL
NOP
NOP
NOP
NOP
tWR
EMRS
NOP
DQS, /DQS
tDS tDH
DQ_in
DT0 OCD adjust mode
DT1
DT2
DT3 OCD calibration mode exit
EO
/CK CK Command
EMRS
Output Impedance Control Register Set Cycle
Drive Mode Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR-II SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after "Enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the "Output Impedance Measurement/Verify Cycle".
High-Z DQS, /DQS
L
NOP tOIT (0 to 32ns) Enter drivemode
NOP
NOP
EMRS
High-Z
Pr
25
DQs High for drive (1) DQs Low for drive (0)
tOIT (0 to 32ns)
DQ
Output Impedance Measurement/Verify Cycle
od
OCD Calibration mode exit
uc t
Preliminary Data Sheet E0203E41 (Ver. 4.1)
EDE5104GASA, EDE5108GASA
Bank Activate Command [ACT] The bank activate command is issued by holding /CAS and /WE High with /CS and /RAS Low at the rising edge of the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through A12 is used to determine which row to activate in the selected bank. The Bank activate command must be applied before any read or write operation can be executed. Immediately after the bank active command, the DDR-II SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCD (min.) is satisfied. Additive latencies of 0, 1 and 2 are supported. Once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is determined by (tRRD).
EO
/CK CK T0 Command
ACT
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
Posted READ
ACT
Posted READ
PRE
PRE
ACT
tRCD(min.)
Address
ROW: 0
COL: 0
ROW: 1
tCCD
COL: 1
ROW: 0
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
tRCD =1
tRRD
Additive latency (AL)
Bank0 Read begins
tRAS tRC
tRP
Pr
Bank1 Active
Bank0 Active
Bank0 Precharge
Bank1 Precharge
Bank0 Active
Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)
od uc t
26
EDE5104GASA, EDE5108GASA
Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS High, /CS and /CAS Low at the clock's rising edge. /WE must also be defined at this time to determine whether the access cycle is a read operation (/WE high) or a write operation (/WE low). The DDR-II SDRAM provides a fast column access operation. A single read or write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 8M bits x 4 I/O x 4 Banks chip has a page length of 2048 bits (defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the column address supplied to the device during the read or write Command (CA0 to CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
EO
-1 /CK CK Command 0
ACT
Posted /CAS Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR-II SDRAM. In this operation, the DDR-II SDRAM allows a /CAS read or write command to be issued immediately after the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is held for the time of the additive latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCD (min), then AL (greater than 0) must be written into the EMRS. The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus /CAS latency (RL=AL+CL).
L
1 2
READ
3
4
5
6
7
8
9
10
11
12
WRIT
AL = 2 DQS, /DQS
CL = 3
WL = RL n-1 = 4
> = tRCD DQ
Read followed by a write to the same bank [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]
Pr
RL = AL + CL = 5
out0 out1 out2 out3
in0 in1 in2 in3
> = tRAC
od
5 6 7 8 9
WRIT WL = RL n-1 = 2
out0 out1 out2 out3
-1
/CK CK Command
0
1
2
3
4
10
11
12
ACT
AL = 0 READ
uc
in0 in1 in2 in3
CL = 3 DQS, /DQS > = tRCD DQ > = tRAC RL = AL + CL = 3
t
Read followed by a write to the same bank [AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
Preliminary Data Sheet E0203E41 (Ver. 4.1)
27
EDE5104GASA, EDE5108GASA
Fixed 4 bits Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. Unlike the DDR-I SDRAM, DDR-II SDRAM supports 4 bits burst mode only. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the DDR-I SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR-I devices, interruption of a burst read or write operation is prohibited. Therefore the burst stop command is not supported on DDR-II SDRAM devices.
[Burst Length and Sequence]
Burst length Starting address (a1, a0) 00 4 01 10 Sequential addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
EO
11
Note: Page length is a function of I/O organization and column addressing 32M bits x 4 organization (CA0 to CA9, CA11, CA12); Page Length = 2048 bits 16M bits x 8 organization (CA0 to CA9, CA11); Page Length = 1024 bits
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L Pr od uc t
28
EDE5104GASA, EDE5108GASA
Burst Read Command [READ] The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set (MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set (EMRS).
T0 /CK CK T1 T2 T3 T4 T5 T6 T7 T8
EO
Command
Posted READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS, /DQS
AL = 2 RL = 5
CL = 3
DQ
out0 out1 out2 out3
L
T0 T1
READ NOP
CL = 3 RL = 3
Burst Read Operation (RL = 5 (AL = 2, CL = 3))
T2
T3
T4
T5
T6
T7
T8
Pr
NOP
NOP
NOP
/CK CK Command
NOP
NOP
NOP
NOP
od
Out0 Out1 Out2 Out3
DQS, /DQS
DQ
Burst Read Operation (RL = 3 (AL = 0 and CL = 3))
uc t
Preliminary Data Sheet E0203E41 (Ver. 4.1)
29
EDE5104GASA, EDE5108GASA
T0 /CK CK Command
Posted READ NOP NOP Posted WRIT NOP NOP NOP NOP NOP
T1
T3
T4
T5
T6
T7
T8
T9
tRTW (Read to Write = 4 clocks)
DQS, /DQS
RL = 5 WL = RL - 1 = 4
DQ
out0 out1 out2 out3
in0
in1
in2
in3
EO
T0 /CK CK Command DQS, /DQS DQ
Burst Read followed by Burst Write (RL = 5, WL = RL-1 = 4)
The minimum time from the burst read command to the burst write command is defined by a read-to-write-turnaround-time, which is 4 clocks.
T1
T2
T3
T4
T5
T6
T7
T8
Enabling a read command at every other clock supports the seamless burst read operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Posted READ NOP
AL = 2
Posted READ
NOP
NOP
NOP
NOP
NOP
NOP
CL = 3 RL = 5
Seamless Burst Read Operation (RL = 5, AL = 2, and CL = 3)
Pr
30
Out0 Out1 Out2 Out3 Out4 Out5 Out6
od
uc t
EDE5104GASA, EDE5108GASA
Burst Write Command [WRIT] The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR).
T0 /CK CK T1 T2 T3 T4 T5 T6 T7 T9
EO
Command
Posted WRIT
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Completion of the Burst Write
DQS, /DQS
WL = RL -1 = 4
>tWR =
DQ
in0
in1
in2
in3
L
T0 /CK CK Command
WRIT
Burst Write Operation (RL = 5, WL = 4, tWR = 3 (AL=2, CL=3))
T1
T2
T3
T4
T5
T6
T7
T9
NOP
Pr
NOP
NOP
NOP
NOP
PRE
NOP
ACT
Completion of the Burst Write
od
>tWR =
DQS, /DQS
WL = RL -1 = 2
>tRP =
DQ
in0
in1
in2
in3
Burst Write Operation (RL = 3, WL = 2, tWR = 2 (AL=0, CL=3))
uc t
Preliminary Data Sheet E0203E41 (Ver. 4.1)
31
EDE5104GASA, EDE5108GASA
T0 /CK CK Command
NOP
Write to Read = CL + 1 + tWTR (2) = 6
T1
T2
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
Posted READ
NOP
NOP
NOP
NOP
DQS, /DQS
AL = 2
WL = RL -1 = 4
CL = 3
RL = 5
>tWTR =
DQ
out0
out1
out2
out3
EO
T0 /CK CK Command
Posted WRIT
Burst Write followed by Burst Read (RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2)
The minimum number of clock from the burst write command to the burst read command is CL + 1 + a write to-readturn-around-time (tWTR). This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array.
T1
T2
T3
T4
T5
T6
T7
T8
L
NOP
Posted WRIT
NOP
NOP
NOP
NOP
NOP
NOP
DQS, /DQS
WL = RL - 1 = 4
Pr
in 0
DQ
in 1
in 2
in 3
in 4
in 5
in 6
in 7
Seamless Burst Write Operation (RL = 5, WL = 4)
Enabling a write command every other clock supports the seamless burst write operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
od
32
uc t
Preliminary Data Sheet E0203E41 (Ver. 4.1)
EDE5104GASA, EDE5108GASA
Write data mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR-II SDRAMs, Consistent with the implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles.
T1 DQS /DQS DQ
T2
T3
T4
T5
T6
in
in
in
in
in
in
in
in
EO
DM
Write mask latency = 0
Data Mask Timing
[tDQSS(min.)] /CK CK
Command
DQS, /DQS
[tDQSS(max.)]
DQS, /DQS DQ DM
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
WRIT
tWR
NOP
tDQSS
NOP
NOP
NOP
NOP
Pr
in0
tDQSS
DQ DM
in2 in3
Data Mask Function, WL = 3, AL = 0 shown
od
in0 in2 in3
uc t
33
EDE5104GASA, EDE5108GASA
Precharge Command [PRE] The precharge command is used to precharge or close a bank that has been activated. The precharge command is triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued. [Bank Selection for Precharge by Address Bits]
A10 L L L L BA0 L H L H x BA1 L L H H x Precharged Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only All banks 0 to 3
EO
H
/CK CK T0 Command DQS, /DQS DQ
Remark: H: VIH, L: VIL, x: VIH or VIL Burst Read Operation Followed by Precharge Minimum read to precharge command spacing to the same bank = AL + 2 clocks For the earliest possible precharge, the precharge command may be issued on the rising edge that is "Additive latency (AL) + 2 clocks" after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.
T1 T2 T3 T4 T5 T6 T7 T8
/CK CK Command
DQS, /DQS
AL = 2
CL = 3
> = tRP
DQ
> = tRAS
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Posted READ
NOP
NOP
PRE
NOP
NOP
NOP
ACT
NOP
AL + 2 clocks
Pr
CL = 3
AL = 1
> = tRP
RL = 4
out0
out1
out2
out3
> = tRAS
CL = 3
Burst Read Operation Followed by Precharge (RL = 4 (AL=1, CL=3))
od
T4 T5 T6
PRE
T0
T1
T2
T3
T7
T8
Posted READ
NOP
NOP
AL + 2 clocks
NOP
NOP
NOP
ACT
NOP
uc
out1
RL = 5
out0
out2
out3
CL = 3
t
Burst Read Operation Followed by Precharge (RL = 5 (AL=2, CL=3))
34
EDE5104GASA, EDE5108GASA
T0 /CK CK Command
Posted READ
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
AL + 2 Clocks
NOP
PRE
NOP
NOP
ACT
NOP
DQS, /DQS
AL = 2
CL = 4
>t = RP
RL = 6
DQ
>t = RAS CL = 4
out0
out1
out2
out3
EO
Burst Read Operation Followed by Precharge (RL = 6 (AL=2, CL=4))
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L Pr od uc t
35
EDE5104GASA, EDE5108GASA
Burst Write followed by Precharge Minimum Write to Precharge Command spacing to the same bank = WL + 2 clocks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR-II SDRAM does not support any burst interrupt operation.
T0 /CK CK Command
Posted WRIT
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
EO
DQS, /DQS DQ
> tWR =
WL = 3
in0
in1
in2
in3
Completion of the Burst Write
L
T0 /CK T1 CK Command
Posted WRIT NOP
Burst Write followed by Precharge (WL = (RL-1) =3)
T2
T3
T4
T5
T6
T7
T9
Pr
NOP
NOP
NOP
NOP
NOP
NOP
PRE
> = tWR
DQS, /DQS
od
in0
in1
in2
in3
WL = 4
DQ
Completion of the Burst Write
Burst Write followed by Precharge (WL = (RL-1) = 4)
uc t
Preliminary Data Sheet E0203E41 (Ver. 4.1)
36
EDE5104GASA, EDE5108GASA
Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto-precharge function. When a read or a write command is given to the DDR-II SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write Command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the autoprecharge function is engaged. During auto-precharge, a read Command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst. Auto-precharge can also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command.
EO
T0 /CK CK
A10 = 1
Burst Read with Auto Precharge [READA] If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR-II SDRAM starts an auto Precharge operation on the rising edge which is (AL + 2) cycles later from the read with AP command when the condition that. When tRAS (min) is satisfied. If tRAS (min.) is not satisfied at the edge, the start point so auto-precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.
L
T1
Posted READ
T2
T3
T4
T5
T6
T7
T8
Pr
NOP NOP
Command
NOP
NOP
NOP
NOP
NOP
ACT
> = tRAS(min.)
DQS, /DQS
AL = 2
CL = 3
od
> = tRP
RL = 5
DQ
> tRC =
out0
out1
out2
out3
CL = 3
uc t
Auto precharge begins
Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRC limit) (RL = 5 (AL = 2, CL = 3, internal tRCD = 3))
Preliminary Data Sheet E0203E41 (Ver. 4.1)
37
EDE5104GASA, EDE5108GASA
T0 /CK CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T8
Command
Posted READ
NOP
NOP > tRAS(min.) =
NOP
NOP
NOP
NOP
ACT
NOP
DQS, /DQS
> = tRP AL = 2 RL = 5 CL = 3
DQ
out0 > = tRC
out1
out2
out3
EO
CL = 3
Auto precharge begins
Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRP limit) RL = 5 (AL = 2, CL = 3, internal tRCD = 3)
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L Pr od uc t
38
EDE5104GASA, EDE5108GASA
Burst Write with Auto-Precharge [WRITA] If A10 is high when a write command is issued, the Write with auto-precharge function is engaged. The DDR-II SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.
T0 /CK CK Command
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T12
Posted WRIT
EO
DQS, /DQS DQ
T0 /CK CK Command
A10 = 1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
WL = RL -1 = 2
> = tWR
in0
> = tRP
in1
in2
in3
> = tRC
L
T3
Posted WRIT
Completion of the Burst Write
Auto Precharge Begins
Burst Write with Auto-Precharge (tRC Limit) (WL = 2, tWR =2, tRP=3)
NOP
Pr
T4 T5 T6
NOP NOP
T7
T8
T9
T12
NOP
NOP
NOP
NOP
ACT
od
> = tWR
in3
DQS, /DQS
WL = RL -1 = 4
> = tRP
DQ
in0
in1
in2
> = tRC
uc
Auto Precharge Begins
Completion of the Burst Write
Burst Write with Auto-Precharge (tWR + tRP) (WL = 4, tWR =2, tRP=3)
t
Preliminary Data Sheet E0203E41 (Ver. 4.1)
39
EDE5104GASA, EDE5108GASA
Automatic Refresh Command (/CAS Before /RAS Refresh) [REF] When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the DDR-II SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the DDR-II SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the Auto Refresh cycle time (tRFC).
T0 /CK CK
High > = tRP > = tRFC > = tRFC
T1
T2
T3
T15
T7
T8
EO
CKE Command
PRE
NOP
NOP
CBR
CBR
NOP
Any Command
Automatic Refresh Command
Self Refresh Command [SELF] The DDR-II SDRAM device has a built-in timer to accommodate Self Refresh operation. The self refresh command is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. Once the Command is registered, CKE must be held low to keep the device in self refresh mode. When the SDRAM has entered self refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during self refresh operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit self refresh operation. Once the clock is cycling, the exit command will be registered asynchronously by bringing CKE high. After CKE is brought high, an internal timer is started to insure CKE is held high for approximately 10ns before registering the self refresh exit command. The purpose of this circuit is to filter out noise glitches on the CKE input that may cause the DDR-II SDRAM to erroneously exit self refresh operation. Once the self refresh command is registered, a delay equal or longer than the tXSC must be satisfied before any command can be issued to the device. CKE must remain high for the entire Self Refresh exit period (tXSC) and commands must be gated off with /CS held High. Alternatively, NOP commands may be registered on each positive clock edge during the self refresh exit interval. (Self Refresh Command)
/CK CK CKE
Command
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
T0 T1
SELF
Pr
T2 T3
Self Refresh Command
od
Tm
> = tXSC
Tn
Tn+1
NOP
Any Command
uc
: VIH or VIL
t
40
EDE5104GASA, EDE5108GASA
Power-Down [PDEN] Power-down is entered when CKE is registered (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, /CK and CKE. In power down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR-II SDRAM, and all other input signals are "VIH or VIL". Power-down duration is limited by the refresh requirements of the device. The power-down state is synchronously exited when CKE is registered High (along with a NOP or DESL). A valid, executable command may be applied after satisfied tXPRD or tXARD for read command exiting form precharge power-down or active power-down respectively ,and after satisfied tXPNR for non-read command.
/CK CK
tIS tIS
EO
CKE Command
VALID
NOP
NOP
VALID
No column access in progress Enter power down mode (Burst read or write operation must not be in progress)
tXPRD, tXPNR Exit tXARD power down mode
: VIH or VIL
Power Down
Burst Interruption Interruption of a burst read or write cycle is prohibited. No Operation Command [NOP] The no operation command should be used in cases when the DDR-II SDRAM is in an idle or a wait state. The purpose of the no operation command is to prevent the DDR-II SDRAM from registering any unwanted commands between operations. A no operation command is registered when /CS is low with /RAS, /CAS, and /WE held high at the rising edge of the clock. A no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command [DESL] The deselect command performs the same function as a no operation command. Deselect Command occurs when /CS is brought high at the rising edge of the clock, the /RAS, /CAS, and /WE signals become don't cares.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Pr
41
od uc t
EDE5104GASA, EDE5108GASA
Package Drawing
60-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
0.2 SA 11.30.1 0.2 SB Unit: mm
0.340.05
0.2
S
0.900.1
ABCDEFGHJKL
EO
12.40.1
INDEX AREA
2.45
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
0.1 S B 123 789 1.6 INDEX MARK 60-0.450.05 0.08
M
S
Pr
0.8 2.2 SAB
od
A 0.8
uc
ECA-TS2-0075-01
t
42
EDE5104GASA, EDE5108GASA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDE51XXGASA. Type of Surface Mount Device EDE51XXGASA: 60-ball FBGA < Lead free (Sn-Ag-Cu) >
EO
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L Pr od uc t
43
EDE5104GASA, EDE5108GASA
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
EO
2 3
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Pr
44
CME0107
od uc t
EDE5104GASA, EDE5108GASA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
EO
Preliminary Data Sheet E0203E41 (Ver. 4.1)
L
Pr
45
M01E0107
od uc t

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